mirror of
https://github.com/FFmpeg/FFmpeg.git
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avcodec/x86/vc1dsp_mc: Move inverse transform into a file of its own
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
This commit is contained in:
Andreas Rheinhardt
@@ -130,7 +130,8 @@ X86ASM-OBJS-$(CONFIG_QPELDSP) += x86/qpeldsp.o \
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x86/fpel.o \
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x86/qpel.o
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X86ASM-OBJS-$(CONFIG_RV34DSP) += x86/rv34dsp.o
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X86ASM-OBJS-$(CONFIG_VC1DSP) += x86/vc1dsp_loopfilter.o \
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X86ASM-OBJS-$(CONFIG_VC1DSP) += x86/vc1dsp_inv_trans.o \
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x86/vc1dsp_loopfilter.o \
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x86/vc1dsp_mc.o x86/fpel.o
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ifdef ARCH_X86_64
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X86ASM-OBJS-$(CONFIG_IDCTDSP) += x86/simple_idct10.o
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121
libavcodec/x86/vc1dsp_inv_trans.asm
Normal file
121
libavcodec/x86/vc1dsp_inv_trans.asm
Normal file
@@ -0,0 +1,121 @@
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;******************************************************************************
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;* VC1 inverse transform
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;* Copyright (c) 2009 Fiona Glaser
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION .text
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%macro INV_TRANS_INIT 0
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movd m0, blockd
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SPLATW m0, m0
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pxor m1, m1
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psubw m1, m0
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packuswb m0, m0
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packuswb m1, m1
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DEFINE_ARGS dest, linesize, linesize3
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lea linesize3q, [linesizeq*3]
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%endmacro
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%macro INV_TRANS_PROCESS 1
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mov%1 m2, [destq+linesizeq*0]
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mov%1 m3, [destq+linesizeq*1]
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mov%1 m4, [destq+linesizeq*2]
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mov%1 m5, [destq+linesize3q]
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paddusb m2, m0
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paddusb m3, m0
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paddusb m4, m0
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paddusb m5, m0
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psubusb m2, m1
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psubusb m3, m1
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psubusb m4, m1
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psubusb m5, m1
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mov%1 [linesizeq*0+destq], m2
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mov%1 [linesizeq*1+destq], m3
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mov%1 [linesizeq*2+destq], m4
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mov%1 [linesize3q +destq], m5
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%endmacro
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; ff_vc1_inv_trans_?x?_dc_mmxext(uint8_t *dest, ptrdiff_t linesize, int16_t *block)
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x4_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x8_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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shl blockd, 2 ; 4 * dc
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lea blockd, [blockq*3+64] ; 12 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x4_dc, 3,4,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x8_dc, 3,3,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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lea blockd, [blockq*3+16] ; 3 * dc + 16
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sar blockd, 5 ; >> 5
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS a
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RET
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@@ -192,100 +192,3 @@ HOR_16B_SHIFT2 OP_PUT, put
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INIT_MMX mmxext
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HOR_16B_SHIFT2 OP_AVG, avg
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%endif ; HAVE_MMX_INLINE
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%macro INV_TRANS_INIT 0
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movd m0, blockd
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SPLATW m0, m0
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pxor m1, m1
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psubw m1, m0
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packuswb m0, m0
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packuswb m1, m1
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DEFINE_ARGS dest, linesize, linesize3
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lea linesize3q, [linesizeq*3]
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%endmacro
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%macro INV_TRANS_PROCESS 1
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mov%1 m2, [destq+linesizeq*0]
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mov%1 m3, [destq+linesizeq*1]
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mov%1 m4, [destq+linesizeq*2]
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mov%1 m5, [destq+linesize3q]
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paddusb m2, m0
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paddusb m3, m0
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paddusb m4, m0
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paddusb m5, m0
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psubusb m2, m1
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psubusb m3, m1
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psubusb m4, m1
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psubusb m5, m1
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mov%1 [linesizeq*0+destq], m2
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mov%1 [linesizeq*1+destq], m3
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mov%1 [linesizeq*2+destq], m4
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mov%1 [linesize3q +destq], m5
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%endmacro
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; ff_vc1_inv_trans_?x?_dc_mmxext(uint8_t *dest, ptrdiff_t linesize, int16_t *block)
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x4_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x8_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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shl blockd, 2 ; 4 * dc
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lea blockd, [blockq*3+64] ; 12 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x4_dc, 3,4,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x8_dc, 3,3,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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lea blockd, [blockq*3+16] ; 3 * dc + 16
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sar blockd, 5 ; >> 5
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS a
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RET
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